Since the scope of the library statement extends over the entire file, it is not necessary to repeat that for the second package. The packages are std_logic_1164 and std_logic_signed and the library is ieee. In most vhdl programs you have already seen examples of packages and libraries. work Specify the name of the desired target library explicit Enables the resolving of ambiguous function overloading You must compile any entities or configurations before an architecture that references them. Compiling a VeriLog Designįor VHDL, the order of compilation is important. To change the current working library, you can use vcom -work and specify the name of the desired target library.
By default, this is the library named work.
The vcom command adds compiled design units to the current working library. Note that the library clause is not used to specify the working library into which the design unit is placed after compilation. You can override this variable by specifying vcom -explicit. Using this variable makes QuestaSim compatible with common industry practice. This variable enables the resolving of ambiguous function overloading in favor of the “explicit” function declaration (not the one automatically created by the compiler for each type declaration). VHDL Procedural Language Application Interface standard (VHDL 1076c-2007) Revised standard (named VHDL 1076 2000, Edition) Mil Std 454 requires comprehensive VHDL descriptions to be delivered with ASICs I realized that the version of ModelSim - Intel 2020.1 starts the simulation without having to modify the vsim command in the file vsim_runner.py, however this error remains in both forms of execution.Initiated by US DoD to address hardware life-cycle crisisĭevelopment of baseline language by Intermetrics, IBM and TI opt/pulp/pulp-sdk/pulp-rt-examples/hello/build/pulp/_rules.mk:182: recipe for target 'run' failed # Time: 0 ps Iteration: 0 Root: / File: NOFILE Design unit '/opt/pulp/pulp/sim/modelsim_libs/tb_lib.tb_pulp' # ** Fatal: (vsim-3381) Obsolete library format for design unit. # ** Note: (vsim-2179) An older version (version 10) DPI tfdb file is being read. # vsim -c -quiet tb_pulp -L models_lib -L vip_lib -t ps "+nowarnTRAN" "+nowarnTSCALE" "+nowarnTFMPC" "+TB_PATH=/opt/pulp/pulp/sim" "+UVM_NO_RELNOTES" -permit_unmatched_virtual_intf "+VSIM_PATH=/opt/pulp/pulp/sim" -gUSE_SDVT_SPI=0 -gUSE_SDVT_CPI=0 -gBAUDRATE=115200 -gENABLE_DEV_DPI=0 -gLOAD_L2=JTAG -gUSE_SDVT_I2S=0 # source /opt/pulp/pulp/sim/tcl_files/run.tcl # source /opt/pulp/pulp/sim/tcl_files/config/run_and_exit.tcl Searching, I saw that the error is related to the version of ModelSim, however when using another version other than 2020.1, the following error appears:
Error loading design in modelsim pro#
I'm using ModelSim - Intel FPGA Pro 2020.1 opt/pulp/pulp-sdk/pulp-rt-examples/time/timer_periodic/build/pulp/_rules.mk:182: recipe for target 'run' failed # ** Error (suppressible): (vsim-19) Failed to access library 'work' at "work". # vsim -c -quiet vopt_tb -L models_lib -L vip_lib -t ps "+nowarnTRAN" "+nowarnTSCALE" "+nowarnTFMPC" "+TB_PATH=/opt/pulp/sim" "+UVM_NO_RELNOTES" -permit_unmatched_virtual_intf "+VSIM_PATH=/opt/pulp/sim" -gUSE_SDVT_SPI=0 -gUSE_SDVT_CPI=0 -gBAUDRATE=115200 -gENABLE_DEV_DPI=0 -gLOAD_L2=JTAG -gUSE_SDVT_I2S=0 # source /opt/pulp/sim/tcl_files/config/run_and_exit.tcl
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